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Fault Tolerant Parity Preserving Reversible Logic

Poornima M.1 , M. S. Suma2

Section:Research Paper, Product Type: Journal Paper
Volume-6 , Issue-11 , Page no. 259-264, Nov-2018

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v6i11.259264

Online published on Nov 30, 2018

Copyright © Poornima M., M. S. Suma . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Poornima M., M. S. Suma, “Fault Tolerant Parity Preserving Reversible Logic,” International Journal of Computer Sciences and Engineering, Vol.6, Issue.11, pp.259-264, 2018.

MLA Style Citation: Poornima M., M. S. Suma "Fault Tolerant Parity Preserving Reversible Logic." International Journal of Computer Sciences and Engineering 6.11 (2018): 259-264.

APA Style Citation: Poornima M., M. S. Suma, (2018). Fault Tolerant Parity Preserving Reversible Logic. International Journal of Computer Sciences and Engineering, 6(11), 259-264.

BibTex Style Citation:
@article{M._2018,
author = {Poornima M., M. S. Suma},
title = {Fault Tolerant Parity Preserving Reversible Logic},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {11 2018},
volume = {6},
Issue = {11},
month = {11},
year = {2018},
issn = {2347-2693},
pages = {259-264},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=3154},
doi = {https://doi.org/10.26438/ijcse/v6i11.259264}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v6i11.259264}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=3154
TI - Fault Tolerant Parity Preserving Reversible Logic
T2 - International Journal of Computer Sciences and Engineering
AU - Poornima M., M. S. Suma
PY - 2018
DA - 2018/11/30
PB - IJCSE, Indore, INDIA
SP - 259-264
IS - 11
VL - 6
SN - 2347-2693
ER -

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Abstract

Reversible logic is the promising design methodology for the future quantum circuits. Since there is no loss in information in reversible circuits, it can be used to create the low power design for super computers. Fault Tolerance in reversible logic is required to ensure the design work correctly even in presence of any faults. A majority voter is proposed which achieves the passive hardware redundancy for any reversible circuit, thereby making the circuit Fault Tolerant. Parity preserving feature induced in the majority voter helps to test the voter for any occurrence of faults. A comparative analysis is done for the available reversible benchmark circuits using the proposed Fault Tolerant approach. A fault diagnosis technique to increase the reliability of the majority voter is also proposed.

Key-Words / Index Term

Fault Tolerance, Quantum, Reversible Logic, Parity Preserving Logic

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