[1] Sheikh.H.F. And Ahmad.I, "Efficient Heuristics for Joint Optimization of Performance, Energy, and Temperature in Allocating Tasks to Multi-core Processors," International Green Computing Conference (IGCC), pp.1-8, Nov 2014.
[2] Xing Yi, Pasricha sudeep, “Soft and Hard Reliability aware scheduling for multicore embedded System with energy harvesting†IEEE Transaction on multiscale computing System, vol. 1, pp no. 220-235, Dec 2015.
[3] Sarma Santanu, Dutt Nikil, "Cross Layer Exploration of heterogeneous Multicore Processor Configuration" 28th International Conference on VLSI Design , pp. 147-152, 2015.
[4] Cuesta David, Acquaviva Andrea, Ayala Jose’L, Hidalgo jose’I, Atienza David, Macii Enrico, "Adaptive Task Migration Policies for Thermal Control in MPSOC’s" ,VLSI 2010 Annual Symposium, pp-110-115, 2010.
[5] Betting.B, Brinkschulte.U, Pacher.M, "Evaluation and Superiority Analysis of a decentralized task control mechanism for dependable real time SOC Architectures," 16th IEEE International symposium on object/component/service oriented Real time distributed computing (ISORC), pp. 1-8, 2013.
[6] Imes Connor, Kim David H.K, Maggio Martina, Hoffmann Henry, "POET: a portable Approach to minimizing energy under soft real time Constraints," 21st IEEE Real time and embedded technology and application Symposium, pp. 75-86, 2015.
[7] Sheikh.H.F. and Ahmad.I, "Simultaneous Optimization of Performance, Energy and Temperature for DAG Scheduling in Multicore Processors," International Green Computing Conference, pp.1-6, June 2012.
[8] Sheikh.H.F and Ahmad.I, "Fast Algorithms for Thermal Constrained Performance Optimization in DAG Scheduling on Multi-Core Processors," 2011 International Green Computing Conference and Workshops (IGCC), pp.1-8, 25-28 July 2011.
[9] Mohammed.R.K, Sahan.R.A, Prabhugoud.M, â€Design Challenges of thermal margining tools for Silicon Validation†12th Intersociety conference on,pp.1-8,2010
[10] Ajami.A.H, Banerjee.K, and Pedram.M, "Modelling and Analysis of Nonuniform Substrate Temperature Effects on Global Ulsi Interconnects," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 849-861, June 2005.
[11] Brest.J, Zumer.V, "A Performance Evaluation of list scheduling heuristics for task graphs without communication costs" Parallel processing, proceeding International workshop on , pp.421-428, 2000.
[12] Zhou.J, Wei.T, Chen.M, Yan.J,†Thermal Aware task scheduling for energy minimization in heterogeneous real time MPSOC system†IEEE Transaction on Computer Aided Design of Integrated circuits and system, pp-1, Nov 2015
[13] Viswananth.R, Wakharkar.V, Watwe.A, and Lebonheur.V, “Thermal Performance Challenges from Silicon to Systems,†Intel Technol. J., Q3, vol. 23, p. 16, 2000.
[14] Kwok Yu Kwong, Ahmad.I†Dynamic Critical Path scheduling: An effective techniques for allocating task graph to multiprocessor†IEEE Transaction on Parallel and Distributed System, vol-7,pp 506-521, Aug 2002
[15]Gui.J, Maskell D.L “A Fast High level event Driven Thermal Estimator for Dynamic Thermal Aware Scheduling†IEEE Transaction on Computer Aided Design of Integrated circuits and systems, vol 31, pp 904-917, June 2012.
[16] C. Hsu and W. Feng. A power-aware run-time system for high- performance computing. In Proceedings of the 2005 ACM/IEEE conference on Supercomputing. IEEE Computer Society washing ton, DC, USA, 2005.
[17] Qinghui Tang, Sandeep K. S. Gupta, and Georgios Varsamopoulos. Energy-Efficient Thermal-Aware Task Scheduling for Homogeneous High-Performance Computing Data Centers: A Cyber-Physical Approach.IEEE Trans. Parallel Distrib. Syst., 19(11):1458{1472, 2008.
[18] Power Consumption curve of an Intel Core i7 950 CPU diagram,http://www.xbitlabs.com/articles/cpu/display/power-consumption-overclocking_11.html,june 3, 2016
VIEWS
PDF 
XML 
