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Power Efficient High Speed Domino Circuit Using Adiabatic Logic

Jeeja Jaculine Let R.B.1 , Bharath P.2 , Varatharaj M.3

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-4 , Page no. 126-130, Apr-2014

Online published on Apr 30, 2014

Copyright © Jeeja Jaculine Let R.B., Bharath P., Varatharaj M. . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Jeeja Jaculine Let R.B., Bharath P., Varatharaj M. , “Power Efficient High Speed Domino Circuit Using Adiabatic Logic,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.4, pp.126-130, 2014.

MLA Style Citation: Jeeja Jaculine Let R.B., Bharath P., Varatharaj M. "Power Efficient High Speed Domino Circuit Using Adiabatic Logic." International Journal of Computer Sciences and Engineering 2.4 (2014): 126-130.

APA Style Citation: Jeeja Jaculine Let R.B., Bharath P., Varatharaj M. , (2014). Power Efficient High Speed Domino Circuit Using Adiabatic Logic. International Journal of Computer Sciences and Engineering, 2(4), 126-130.

BibTex Style Citation:
@article{R.B._2014,
author = {Jeeja Jaculine Let R.B., Bharath P., Varatharaj M. },
title = {Power Efficient High Speed Domino Circuit Using Adiabatic Logic},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {4 2014},
volume = {2},
Issue = {4},
month = {4},
year = {2014},
issn = {2347-2693},
pages = {126-130},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=121},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=121
TI - Power Efficient High Speed Domino Circuit Using Adiabatic Logic
T2 - International Journal of Computer Sciences and Engineering
AU - Jeeja Jaculine Let R.B., Bharath P., Varatharaj M.
PY - 2014
DA - 2014/04/30
PB - IJCSE, Indore, INDIA
SP - 126-130
IS - 4
VL - 2
SN - 2347-2693
ER -

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Abstract

In this paper, a new domino circuit is proposed, inorder to have lower power consumption.For this proposed technique which is implemented based on adiabatic logic.The proposed circuit technique decreases the parasitic capatance in the dynamic node,to have fast and robust circuits.Thus the leakage current and consecuently power consumption and delay are reduced.Simulation results shown the effeciency and effectiveness of the domino circuit.The domino circuit designed using adiabatic logic will reduce the power consumption.

Key-Words / Index Term

Domino Logic, Adiabatic Logic,Leakage Current

References

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