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Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic

Nandhini M.1 , Muralidharan V.2 , Varatharaj M.3

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-4 , Page no. 131-135, Apr-2014

Online published on Apr 30, 2014

Copyright © Nandhini M., Muralidharan V., Varatharaj M. . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Nandhini M., Muralidharan V., Varatharaj M., “Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.4, pp.131-135, 2014.

MLA Style Citation: Nandhini M., Muralidharan V., Varatharaj M. "Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic." International Journal of Computer Sciences and Engineering 2.4 (2014): 131-135.

APA Style Citation: Nandhini M., Muralidharan V., Varatharaj M., (2014). Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic. International Journal of Computer Sciences and Engineering, 2(4), 131-135.

BibTex Style Citation:
@article{M._2014,
author = {Nandhini M., Muralidharan V., Varatharaj M.},
title = {Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {4 2014},
volume = {2},
Issue = {4},
month = {4},
year = {2014},
issn = {2347-2693},
pages = {131-135},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=122},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=122
TI - Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic
T2 - International Journal of Computer Sciences and Engineering
AU - Nandhini M., Muralidharan V., Varatharaj M.
PY - 2014
DA - 2014/04/30
PB - IJCSE, Indore, INDIA
SP - 131-135
IS - 4
VL - 2
SN - 2347-2693
ER -

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Abstract

To design a data flip-flop consistent with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption and also reduce the power dissipation replacing the discharge and evaluation phase by pull up and pull down networks using Reverse Logic. A part of an encryption algorithm is used as case a study to prove the effectiveness of the proposed circuit. Simulation results in a 65 nm CMOS process show an improvement in the energy consumption and power consumption.

Key-Words / Index Term

Differential Power Analysis (DPA), Dual-Rail Logic, Security, Reverse Logic, Three-Phase Dual-Rail Pre-Charge Logic (TDPL)

References

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