Open Access   Article Go Back

Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic

Nandhini M.1 , Muralidharan V.2 , Varatharaj M.3

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-4 , Page no. 131-135, Apr-2014

Online published on Apr 30, 2014

Copyright © Nandhini M., Muralidharan V., Varatharaj M. . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

View this paper at   Google Scholar | DPI Digital Library

XML View
PDF Download

How to Cite this Paper

  • IEEE Citation
  • MLA Citation
  • APA Citation
  • BibTex Citation
  • RIS Citation

IEEE Style Citation: Nandhini M., Muralidharan V., Varatharaj M., “Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.4, pp.131-135, 2014.

MLA Style Citation: Nandhini M., Muralidharan V., Varatharaj M. "Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic." International Journal of Computer Sciences and Engineering 2.4 (2014): 131-135.

APA Style Citation: Nandhini M., Muralidharan V., Varatharaj M., (2014). Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic. International Journal of Computer Sciences and Engineering, 2(4), 131-135.

BibTex Style Citation:
@article{M._2014,
author = {Nandhini M., Muralidharan V., Varatharaj M.},
title = {Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {4 2014},
volume = {2},
Issue = {4},
month = {4},
year = {2014},
issn = {2347-2693},
pages = {131-135},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=122},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=122
TI - Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic
T2 - International Journal of Computer Sciences and Engineering
AU - Nandhini M., Muralidharan V., Varatharaj M.
PY - 2014
DA - 2014/04/30
PB - IJCSE, Indore, INDIA
SP - 131-135
IS - 4
VL - 2
SN - 2347-2693
ER -

VIEWS PDF XML
3474 3335 downloads 3695 downloads
  
  
           

Abstract

To design a data flip-flop consistent with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption and also reduce the power dissipation replacing the discharge and evaluation phase by pull up and pull down networks using Reverse Logic. A part of an encryption algorithm is used as case a study to prove the effectiveness of the proposed circuit. Simulation results in a 65 nm CMOS process show an improvement in the energy consumption and power consumption.

Key-Words / Index Term

Differential Power Analysis (DPA), Dual-Rail Logic, Security, Reverse Logic, Three-Phase Dual-Rail Pre-Charge Logic (TDPL)

References

[1] Marco Bucci, Luca Giancane, Raimondo Luzzi, and Alessandro Trifiletti (2012) introduced, the �a flip-flop for the dpa resistant three-phase dual-rail pre-charge logic family�, in proc. ieee int. on very large scale integration system pp. 2128�2132.
[2] P.Kocher, J. Jaffe, And B. Jun, �Differential Power Analysis,� In Proc.Adv. Cryptol. (Crypto), 1999, Pp. 388�397.
[3] K. Tiri, M. Akmal, and I. Verbauwhede, �A dynamic and differentialCMOS logic with signal independent power consumption to withstand differential power analysis on smart in Proc. IEEE 28th Euro.Solid-State Circuit Conf. (ESSCIRC), 2002, pp. 403�406.
[4] D. Sokolov, J. Murphy, A. Bystrov, and A. Yakovlev, �Improving the security of dual-rail circuits,� in Proc. Workshop Cryptograph. Hardw.Embed cards,� in Proc. IEEE 28th Euro.Solid-State Circuit Conf. (ESSCIRC), 2002, pp. 403�406.
[5] K. Tiri and I. Verbauwhede, �A logic design methodology for a secure DPA resistant ASIC or FPGA implementation,� in Proc. Design,Autom., Test Euro. Conf. Expo. (DATE), 2004, pp. 246�251.. Syst. (CHES), 2004, pp. 282�297.
[6] K. Tiri and I. Verbauwhede, �Place and route for secure standard cell design,� in Proc. Smart Card Res. Adv. Appl. IFIP Conf. (CARDIS),2004, pp. 143�158.
[7] T. Popp and S. Mangard, �Masked dual-rail pre-charge logic: DPA-resistance without routing constraints,� in Proc. Workshop Cryptograph.Hardw. Embed. Syst. (CHES), 2005, pp. 172�186.
[8] T.PoppandS.Mangard,�ImplementationaspectsoftheDPA-resistantlogic style MDPL,� in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS),2006, pp. 2913�2916.

[9] T. Popp, M. Kirschbaum, T. Zefferer, and S. Mangard, �Evaluation of the masked logic style MDPL on a prototype chip,� in Proc. Workshop Cryptograph. Hardw. Embed. Syst. (CHES), 2007, pp. 81�94.
[10] M. Bucci, L. Giancane, R. Luzzi, and A. Trifiletti, �Three-phase dual-railpre chargelogic,�in Proc.Workshop Cryptograph.Hardw Embed.Syst. (CHES), 2006, pp. 232�241.
[11] E. Menendez and K. Mai, �Ahigh-performance, low-overhead,power-analysis-resistant, single-rail logic style,� in Proc. IEEE Int. Workshop Hardw.-Oriented Security Trust (HOST), 2008, pp. 33�36.
[12] R. Anderson, E. Biham, and L. Knudsen, �Serpent: A Proposal for theAdvanced Encryption Standard,� NIST AES proposal, 1998. [Online].Available:http://www.cl.cam.ac.uk/ftp/users/ria14/serpent.pdf
[13] F. Regazzoni, T. Eisenbarth, A. Poschmann, J. Gro�sch�dl, F.Gurkaynak, M. Macchetti, Z. Toprak, L. Pozzi, C. Paar, Y. Leblebici,and P. Ienne, �Evaluating resistance of MCML technology to poweranalysis attacks using a simulation-based methodology,� Trans. Computation. Sci. IV, vol. 5430, pp. 230�243, 2009.
[14] K. J. Kulikowski, M. Su, A. Smirnov, A. Taubin, M. G. Karpovsky,and D. MacDonald, �Delay insensitive encoding and power analysis:A balancing act,� in Proc. 11th IEEE Int. Symp. Asynch. Circuits Syst.(ASYNC), 2005, pp. 116�125.
[15] K. J. Lin, S. C. Fang, S. H. Yang, and C. C. Lo, �Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware,� in Proc. Conf. Exhib. Design, Autom. Test Euro. (DATE),2007, pp. 1�6.
[16] K. J. Kulikowski, M. G. Karpovsky, and A. Taubin, �Power attacks on secure hardware based on early propagation of data,� in Proc. 12th IEEE Int. On-Line Test. Symp., 2006, pp. 131�138.
[17] K. Tiri and I. Verbauwhede, �Design method for constant power con-sumption of differential logic circuits,� in Proc. Conf. Exhib. Design,Autom., Test Euro. (DATE), 2005, pp. 628�633.