Recently, reconfigurable digital image processing algorithm has become growing research area in field of real-time embedded system. The edge detection algorithms are one of key area in digital image processing for object recognition or detection. These algorithms are usually implemented in software but it can be also implemented in hardware for special purpose such as high computational speed and good accuracy. This paper describes the Sobel edge detection algorithm has been designed using Hardware Description Language (HDL) and then implemented it on Field Programmable Gate Array (FPGA) devices with an emphasis on the salient features of FPGA technology. The result analysis shows that hardware implementing Sobel edge operator provide higher speed compare to software simulation. The proposed implementation uses a modified architecture which effectively reduces hardware resources. The images are transferred from PC to FPGA device using UART serial communication. The FPGA device processes the given design and result back to the PC. In PC both the results are verified.

Edge Detection, FPGA, Sobel Operator, VHDL,MATLAB

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