Open Access   Article Go Back

FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog

Harsh H. Ghelani1 , Nilesh L. Jha2 , Rohan Naik3 , Pragya Gupta4

  1. Electronics Dept, KJ Somaiya College of Engineering,Mumbai, India.
  2. Electronics Dept, KJ Somaiya College of Engineering,Mumbai, India.
  3. Electronics Dept, KJ Somaiya College of Engineering,Mumbai, India.
  4. Electronics Dept, KJ Somaiya College of Engineering,Mumbai, India.

Section:Research Paper, Product Type: Journal Paper
Volume-6 , Issue-4 , Page no. 143-146, Apr-2018

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v6i4.143146

Online published on Apr 30, 2018

Copyright © Harsh H. Ghelani, Nilesh L. Jha, Rohan Naik, Pragya Gupta . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

View this paper at   Google Scholar | DPI Digital Library

XML View
PDF Download

How to Cite this Paper

  • IEEE Citation
  • MLA Citation
  • APA Citation
  • BibTex Citation
  • RIS Citation

IEEE Style Citation: Harsh H. Ghelani, Nilesh L. Jha, Rohan Naik, Pragya Gupta, “FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog,” International Journal of Computer Sciences and Engineering, Vol.6, Issue.4, pp.143-146, 2018.

MLA Style Citation: Harsh H. Ghelani, Nilesh L. Jha, Rohan Naik, Pragya Gupta "FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog." International Journal of Computer Sciences and Engineering 6.4 (2018): 143-146.

APA Style Citation: Harsh H. Ghelani, Nilesh L. Jha, Rohan Naik, Pragya Gupta, (2018). FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog. International Journal of Computer Sciences and Engineering, 6(4), 143-146.

BibTex Style Citation:
@article{Ghelani_2018,
author = {Harsh H. Ghelani, Nilesh L. Jha, Rohan Naik, Pragya Gupta},
title = {FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {4 2018},
volume = {6},
Issue = {4},
month = {4},
year = {2018},
issn = {2347-2693},
pages = {143-146},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=1859},
doi = {https://doi.org/10.26438/ijcse/v6i4.143146}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v6i4.143146}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=1859
TI - FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog
T2 - International Journal of Computer Sciences and Engineering
AU - Harsh H. Ghelani, Nilesh L. Jha, Rohan Naik, Pragya Gupta
PY - 2018
DA - 2018/04/30
PB - IJCSE, Indore, INDIA
SP - 143-146
IS - 4
VL - 6
SN - 2347-2693
ER -

VIEWS PDF XML
711 453 downloads 299 downloads
  
  
           

Abstract

The proffered paper is presented on the practical implementation of a Configurable Linear Feedback Shift Register using Verilog and assesses its various parameters with respect to its configurable aspects and physical performance. The practical implementation is configurable with respect to Number of Bits, Seed Value, Number of Taps and Tap Position that increases the randomness of the output thus creating a more pseudo-random cycle. Moreover, reversible logic is explored and analysed and the technology is comprehended in this paper as an emerging technology that can be used to implement the designed Configurable Linear Feedback Shift Register. Reversible logic is said to enhance the power efficiency of a logical circuit than the conventional models and thus eases the migration to emerging technologies of Quantum Computing, Portable Embedded Systems and Low Power VLSI. The chosen target for the hardware realization of the CLFSR is Altera Cyclone II FPGA. Furthermore, simulation and synthesis of the design is done using ModelSim-Altera for Quartus II 12.1 Web Edition.

Key-Words / Index Term

Configurable Linear Feedback Shift Register, Field Programmable Gate Array, Verilog, Reversible Logic, Shift Register, Random Number Generator.

References

[1] Efficient Shift Registers, LFSR Counters, and Long Pseudo- Random Sequence Generators, Application Note, Xilinx Inc.
[2] S Mishra, R Tripathi and D Tripathi, “Implementation of Configurable Linear Feedback Shift Register in VHDL” 9781-1-5090-2118-5/16/$31.00 ©2016 IEEE
[3] Lama Shaer, Tarek Sakakini, Rouwaida Kanj, Ali Chehab and Ayman Kayssi,” A Low Power Reconfigurable LFSR ”18th Mediterranean Electrotechnical Conference MELECON 2016, Limassol, Cyprus, 18-20 April 2016
[4] C. H. Bennett, R. Landauer, “The fundamentals physical limits of computation”.
[5] H. Thapliyal, M. B. Srinivas, M Zwolinski, A beginning in the reversible logic synthesis of sequential circuits. In proceedings of the Int. Conf. on the military & Aerospace Programmable Logic devices, 2005.
[6] J. Rice, “A new look at reversible memory elements”, In proceedings of the International Symposium on circuit and systems. 243-246, 2006.
[7] K. Morita, “Reversible computing and cellular automata- a survey”, Elsevier Theor. Compt. Sci. 395, 1, 101-131, 2008.
[8] Efficient LFSR, XILINX, XAPP 052 July 7,1996 (Version 1.1)
[9] P. Kaye, R. Laflamme, M. Mosca, An Introduction to Quantum Computing. Oxford University Press Inc., Oxford, 2007
[10] P. Yelekar, S. Chiwande, Introduction to reversible logic gates and its applications, 2nd National Conference on Information and Communication Technology (NCICT) 2011, proceedings published in International Journal of Computer Applications (IJCA)
[11] Reversible logic synthesis methodologies with applications to quantum computing, Springer Publication, 2016, ISBN: 978-3-319-23478-6