Network-on-Chips (NoCs) are rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chips using low power overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topology have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. The performance of topology can be analyzed based on power and latency; the power consumption and the latency in Network-on-Chip (NoC) are two challenging objectives. In this paper, we proposed on Clustering-Based Topology Generation and disable nodes to construct routers a torus based clustered topology methods for power saving and performances aware on NoC. Experimental results show that the approach saves proposed method consume less power consumption on average in comparison with using torus topology and achieves significant topology performance improvement.

NoCs, Cluster, topology generation, disable notes, Routers

[1] K. Venkatasuresh, K. Bala , "Design and Verification of Five Port Router for Network on Chip Using VERILOG", International Journal of Computer Sciences and Engineering, Vol.2, Issue.9, pp.78-80, 2014.
[2] Abdul Quaiyum Ansari, Mohammad Rashid Ansari, and Mohammad Ayoub Khan. “Performance evaluation of various parameters of network-on-chip for different topologies”.INDICON, Annual IEEE, pages 1–4,2015.
[3] G. Leary, K. Srinivasan, K. Mehta and K. S. Chatha, “Design of network on chip architectures with a genetic algorithm-based technique,” IEEE Trans. on Very Large Scale Integration Systems, vol. 17, no. 5, pp. 674-687, 2009 .
[4] Z. Liu, J. Cai, L. Yao and M. Du, “Application-aware generation and optimization for NoC topology,” in Proc. IEEE Youth Conf. Information, Computing and Telecommunication, pp. 259-262, 2009.
[5] K. C. Chang and T. F. Chen, “Low-power algorithm for automatic topology generation for application- specific networks on chips,” IET Computers & Digital Techniques, vol. 2, no. 3, pp. 239-249, 2008.
[6] Y. Ar, S. Tosun, and H. Kaplan, “TopGen: a new algorithm for automatic topology generation for network on chip architectures to reduce power consumption,” in Proc. AICT, pp.1-5,2009.
[7] F. Ge and N. Wu, “Genetic algorithm based mapping and routing approach for network on chip architectures,” Chinese Journal of Electronics, vol.19, no.1, pp. 91-96, Jan. 2010.
[8] N. Y. Phing, M. N. M. Warip, P. Ehkan, and S. Y. Teo, “Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method,” vol. 10, no. 2, pp. 514–520, 2018.
[9] D. Systems, A. S. Hassan, A. A. Morgan, and M. W. El-kharashi, “Clustered Networks-on-Chip:Simulation and Performance Evaluation,” vol. 2, no. 2, 2017.
[10] M. Deivakani and D. Shanthi, “Design of Efficient Router with Low Power and Low Latency for Network on Chip,” no. April, pp. 339–349, 2016.
[11] S. Bansal, H. K. Mondal, S. H. Gade, and S. Deb, “Energy Efficient NoC Router for High Throughput Applications in Many-Core GPUs,” 2017 IEEE Int. Symp. Nanoelectron. Inf. Syst., pp. 50–55, 2017.