Open Access   Article Go Back

Analysis of Power Consumptions in 8 Port NOC Router for Different Topologies

L. Bobinson Singha1 , Champa Tanga2

Section:Research Paper, Product Type: Journal Paper
Volume-6 , Issue-6 , Page no. 930-935, Jun-2018

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v6i6.930935

Online published on Jun 30, 2018

Copyright © L. Bobinson Singha, Champa Tanga . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

View this paper at   Google Scholar | DPI Digital Library

How to Cite this Paper

  • IEEE Citation
  • MLA Citation
  • APA Citation
  • BibTex Citation
  • RIS Citation

IEEE Style Citation: L. Bobinson Singha, Champa Tanga, “Analysis of Power Consumptions in 8 Port NOC Router for Different Topologies,” International Journal of Computer Sciences and Engineering, Vol.6, Issue.6, pp.930-935, 2018.

MLA Style Citation: L. Bobinson Singha, Champa Tanga "Analysis of Power Consumptions in 8 Port NOC Router for Different Topologies." International Journal of Computer Sciences and Engineering 6.6 (2018): 930-935.

APA Style Citation: L. Bobinson Singha, Champa Tanga, (2018). Analysis of Power Consumptions in 8 Port NOC Router for Different Topologies. International Journal of Computer Sciences and Engineering, 6(6), 930-935.

BibTex Style Citation:
@article{Singha_2018,
author = {L. Bobinson Singha, Champa Tanga},
title = {Analysis of Power Consumptions in 8 Port NOC Router for Different Topologies},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {6 2018},
volume = {6},
Issue = {6},
month = {6},
year = {2018},
issn = {2347-2693},
pages = {930-935},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=2276},
doi = {https://doi.org/10.26438/ijcse/v6i6.930935}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v6i6.930935}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=2276
TI - Analysis of Power Consumptions in 8 Port NOC Router for Different Topologies
T2 - International Journal of Computer Sciences and Engineering
AU - L. Bobinson Singha, Champa Tanga
PY - 2018
DA - 2018/06/30
PB - IJCSE, Indore, INDIA
SP - 930-935
IS - 6
VL - 6
SN - 2347-2693
ER -

VIEWS PDF XML
632 311 downloads 142 downloads
  
  
           

Abstract

The network on chip (NoC) has replace traditional system on chip (SoC) to meet the communication requirement. The communication on NoC chip is carried out by means of router. For implementing better NoC, the router should be efficiently designed. The paper reviews NoC router and NoC parameters which affects the router design. Design of NoC router depends on network topology, switching techniques and routing algorithm. The Eight port router for different topology design is synthesized and simulated using Verilog code. A comparative study is made on the based of power analyses for different topologies of the 8 port NoC router. It is observed that design of 8 port routers of Octagon, Mesh, Ring, Star, and Torus are having same leakage power. It has been observed that Star topology is less in power consumption as compared to Octagon, Mesh, Ring, Torus and Fat tree topology for 8port NoC router.

Key-Words / Index Term

Network on chip (NOC), Systen on Chip(SOC), Topologies

References

M. Palesi, R.Holsmark, S. Kumar, and V. Catania, “Application-specific routing algorithms for a network on chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 20, no3 pp. 316-339, 2009
[2] L. Benini and D. Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, vol.35 pp.70-78(2002).
[3] V. Dumitriu and G. N. Khan, “Throughput- oriented NOC topology generation and analysis for high-performance SOC,” IEEE Transactions on VLSI Systems, vol. in press 2009.
[4] A. Chien, “A cost and speed model for k-ary n-Cube Wormhole Routers,” IEEE Transactions on Parallel and Distributed Systems, vol.9, no2, pp.29-36, Feb 1998.
[5] B. H. Meyer, J.J. Pieper, J.M. Paul, J.E. Nelson, S. M. Pieper and A.G.Rowe, “Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors,” IEEE transactions on Computers, vol.54, no. 6, pp.684-697, Jun 2005.
[6] L. S. Peh and W. J. Dalley, A delay model for router microarchitectures,” IEEE Micro, vol.21, no. 1, pp. 26-34, Jan. 2001.
[7] T. Bjerregaard and K. Mahadevan, “A survey of research and practices of network-on-chip,”ACM Computing Surveys, vol. 38, pp.38, pp.1-51, Mar. 2006.
[8] V. Pavlidis and E. Friedman,” Interconnect-based design methodologies for three-dimensional integrated circuits’’ Proceeding of the IEEE, vol.97, no.1, pp.123-140, 2009.
[9] H. Elmiligi, A. Morgan, M. W. EI-Kharashi, and F. Gebli, “ Power Aware Topology Optimization for Network-on-chips,” in a proceeding of the IEEE International Symposium on Circuits and SystemsConference on Design and Test of Integrated Systems in Nanoscale Technology, Era Cario, Egypt, Apr. 6-9, 2009, pp.107-112.
[10] Axel Jantsch and Hannu Tenhunen(Eds.), Networks on a chip, Kluwer Academic Publishers, 2003
[11] A Delay-Aware Topology-based Design for Network-on-chip Applications By Haytham Elmiligi, Ahmed A. Morgan, M. Watheq El-Kharashi, Fayez Gebali.IEEE transaction, 2009.
[12] Khalid Latif, Tiberiu Seceleanu, Hannu Tenhunen, “Power and Area Efficient Design of Network-on-Chip Router Through Utilization of Idle Buffers”, In the proceedings of the 2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems.
[13] Cheng Liu•, Liyi Xiao, Fangfa Fu, Design and “Analysis of On-Chip Router”, IJCTT, Aug 2011
[14] W. Zhou, Y. Zhang, and Z. Mao,” An application specific NOC mapping for the optimized delay,” in a proceeding of the IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia , Sept. 5-7, 2006, pp. 184-188.
[15] M. Nickray, M.Dehyadgari, and A. Afzali-kusha, “Power and Delay optimization for a network on chip,” in Proceedings of the 2005 European Conference on Circuit Theory and Designs, Cork, Ireland, Aug-28-2 Sept. 2005, pp. 273-276.
[16] H. Elmiligi, A. A. Morgan, M. W. EI-Kharashi and F. Gebli, “ A reliability-aware design methodology for network-on-chip applications,” in proceeding of the IEEE International Conference on Design and Test of Integrated Systems in Nano scale Technology ,Era Cario, Egypt, Apr. 6-9, 2009, pp. 107-112.
[17] M. Mirza-Aghatabar+,S.Koohi+, S. Hessabi*, M. Pedram†,” An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models”, IEEE International Conference on Digital System DSD 2007.
[18] Victor Dumitriu and Gul N. Khan, ”Throughput-Oriented NoC Topology Generation and Analysis for High-Performance SoCs”, IEEE transactions on very large scale integration (vlsi) systems, vol. 17, no. 10, october 2009.
[19] Mahmoud Moadeli1, Ali Shahrabi2, Wim Vanderbauwhede1, Mohamed Ould-Khaoua1,” An Analytical Performance Model for the Spidergon NoC”, IEEE 21st International Conference on Advanced Networking and Applications (AINA`07) 2007.
[20] Ville Rantala, Teijo Lehtonen, Juha Plosila, ‘Network on Chip Routing Algorithms,” Journal of Systems Architecture, TUCS Technical Report No 779, pp. 5-7, August 2006
[21] K.Shiney, .K.V.Subrahmanyam and S Chandra Sekhar “High throughput compact delay-insensitive asynchronous NoC router” IJCSE, October 2014