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To Design Low power Magnitude Comparator using CMOS Technology

M.N. Vaidya1 , S.R. Patil2

Section:Research Paper, Product Type: Journal Paper
Volume-6 , Issue-6 , Page no. 936-939, Jun-2018

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v6i6.936939

Online published on Jun 30, 2018

Copyright © M.N. Vaidya, S.R. Patil . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: M.N. Vaidya, S.R. Patil, “To Design Low power Magnitude Comparator using CMOS Technology,” International Journal of Computer Sciences and Engineering, Vol.6, Issue.6, pp.936-939, 2018.

MLA Style Citation: M.N. Vaidya, S.R. Patil "To Design Low power Magnitude Comparator using CMOS Technology." International Journal of Computer Sciences and Engineering 6.6 (2018): 936-939.

APA Style Citation: M.N. Vaidya, S.R. Patil, (2018). To Design Low power Magnitude Comparator using CMOS Technology. International Journal of Computer Sciences and Engineering, 6(6), 936-939.

BibTex Style Citation:
@article{Vaidya_2018,
author = {M.N. Vaidya, S.R. Patil},
title = {To Design Low power Magnitude Comparator using CMOS Technology},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {6 2018},
volume = {6},
Issue = {6},
month = {6},
year = {2018},
issn = {2347-2693},
pages = {936-939},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=2277},
doi = {https://doi.org/10.26438/ijcse/v6i6.936939}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v6i6.936939}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=2277
TI - To Design Low power Magnitude Comparator using CMOS Technology
T2 - International Journal of Computer Sciences and Engineering
AU - M.N. Vaidya, S.R. Patil
PY - 2018
DA - 2018/06/30
PB - IJCSE, Indore, INDIA
SP - 936-939
IS - 6
VL - 6
SN - 2347-2693
ER -

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Abstract

This paper presents a low power 2 bit magnitude comparator. The speed and power of comparator have important influence on performance of complex arithmetic and logical circuitries such as ADC, Memory chips etc. It plays a vital role in various DSP, high speed data processors, microprocessors, microcontroller based applications. The proposed comparator design is compared with different logic styles such as PTL, Domino logic, and Transmission gates with voltage sweep. The simulations are carried out on Mentor Graphics (ELDO tool) using 90 nm technology and in Micowind using 180 nm technologies. Simulation is done on 0.6V, 0.8V, 1V and 1.2V respectively. It is found that power is least dissipates in 0.6 V that is 48.82pW.but it has the longest delay of 53.098ns.The simulation results of proposed design using 90 nm technology show improvement in power delay product, 60.26% in greater than circuit, 56.14% in lesser than circuit and 59.48% in equals to function.

Key-Words / Index Term

Magniude Comparator, CMOS technology, Domino logic, PDP,Coupling

References

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