In this paper, The Juctionless Double Gate Vertical MOSFET with metal gate electrode and high-k gate dielectric material (HfO2) has been analyzed using simulation tool. The simulated results show significant improvement in its performance. In this device structure, the metal gate electrode and high-k gate dielectric material (HfO2) are used at the place of polysilicon gate electrode and SiO2 layer. We observed that use of metal gate electrode with SiO2 in JLVMOS exhibits drain current (Idmax) of 0.98 mA, average sub-threshold swing 67mV/dec and DIBL 61mV/V at gate voltage of 1V. When high-k gate dielectric material (HfO2) is used with metal gate electrode in JLVMOS shows drain current (Idmax) of 1.7mA, average subthreshold swing 61mV/dec and DIBL 40mV/V at gate voltage of 1V. This improvements in the performance of JLVMOS using high-k material can be utilized for high performance circuit applications.

Junctionless Double Gate Vertical MOSFET (JLVMOS), Subthreshold swing (S.Swing), Drain Induced Barrier Lowering (DIBL), HfO2, Workfuntion (WF)

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