IEEE Style Citation: K. Venkatasuresh, K. Bala , “Design and Verification of Five Port Router for Network on Chip Using VERILOG,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.9, pp.78-80, 2014.
MLA Style Citation: K. Venkatasuresh, K. Bala "Design and Verification of Five Port Router for Network on Chip Using VERILOG." International Journal of Computer Sciences and Engineering 2.9 (2014): 78-80.
APA Style Citation: K. Venkatasuresh, K. Bala , (2014). Design and Verification of Five Port Router for Network on Chip Using VERILOG. International Journal of Computer Sciences and Engineering, 2(9), 78-80.
BibTex Style Citation:
@article{Venkatasuresh_2014,
author = {K. Venkatasuresh, K. Bala },
title = {Design and Verification of Five Port Router for Network on Chip Using VERILOG},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {9 2014},
volume = {2},
Issue = {9},
month = {9},
year = {2014},
issn = {2347-2693},
pages = {78-80},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=258},
publisher = {IJCSE, Indore, INDIA},
}
RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=258
TI - Design and Verification of Five Port Router for Network on Chip Using VERILOG
T2 - International Journal of Computer Sciences and Engineering
AU - K. Venkatasuresh, K. Bala
PY - 2014
DA - 2014/10/04
PB - IJCSE, Indore, INDIA
SP - 78-80
IS - 9
VL - 2
SN - 2347-2693
ER -
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Abstract
The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the five port router for network on chip using the latest verification methodologies, Hardware Verification Languages and EDA tools and qualifies the Design for Synthesis an implementation. This Router design contains Four output ports and one input port, it is packet based Protocol. This Design consists Registers, Fsm and FIFO�s.For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time multiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized time multiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration.
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