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FPGA Implementation for Fractal Quadtree Image Compression

S. Padmavati1 , Vaibhav Meshram2

Section:Research Paper, Product Type: Journal Paper
Volume-6 , Issue-10 , Page no. 405-409, Oct-2018

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v6i10.405409

Online published on Oct 31, 2018

Copyright © S. Padmavati, Vaibhav Meshram . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: S. Padmavati, Vaibhav Meshram, “FPGA Implementation for Fractal Quadtree Image Compression,” International Journal of Computer Sciences and Engineering, Vol.6, Issue.10, pp.405-409, 2018.

MLA Style Citation: S. Padmavati, Vaibhav Meshram "FPGA Implementation for Fractal Quadtree Image Compression." International Journal of Computer Sciences and Engineering 6.10 (2018): 405-409.

APA Style Citation: S. Padmavati, Vaibhav Meshram, (2018). FPGA Implementation for Fractal Quadtree Image Compression. International Journal of Computer Sciences and Engineering, 6(10), 405-409.

BibTex Style Citation:
@article{Padmavati_2018,
author = {S. Padmavati, Vaibhav Meshram},
title = {FPGA Implementation for Fractal Quadtree Image Compression},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {10 2018},
volume = {6},
Issue = {10},
month = {10},
year = {2018},
issn = {2347-2693},
pages = {405-409},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=3038},
doi = {https://doi.org/10.26438/ijcse/v6i10.405409}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v6i10.405409}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=3038
TI - FPGA Implementation for Fractal Quadtree Image Compression
T2 - International Journal of Computer Sciences and Engineering
AU - S. Padmavati, Vaibhav Meshram
PY - 2018
DA - 2018/10/31
PB - IJCSE, Indore, INDIA
SP - 405-409
IS - 10
VL - 6
SN - 2347-2693
ER -

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Abstract

The growth of digital technology over the past decades is leading to new challenges like storage and transmission of digital images. As the digital image in its raw form occupies more storage space and takes longer time for transmission. Several image compression methods exist to address this issue and fractal image compression is one among the popular image compression methods. But fractal image compression has a disadvantage of more encoding time. In this paper, we have proposed a new architecture for fractal image compression. The proposed architecture is modeled using Verilog HDL, synthesized using Xilinx ISE 14.2, implemented on Xilinx Spartan 6 FPGA board and is tested on Standard Lena image[512x512]. The proposed architecture will reduce the design cycle time and the implementation cost. The results of the proposed architecture have shown a considerable reduction in encoding time to 5.897ns when compared to software implementation.

Key-Words / Index Term

Architecture, Fractal Image Compression, FPGA, Quadtree Decomposition

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