A Multiplier is one of the essential components in the embedded system and digital signal processing (DSP) applications like digital filtering, digital communications, digital image processing, and spectral analysis etc. Parallel multiplication concept was implemented earlier to achieve higher speed. But in order to design an effective multiplier, speed is not the only consideration, area and power also must be taken into account while designing a circuit. To achieve this, a new technique has been introduced here for fast multiplication of two numbers. Inputs are separated into partitions where one number is again separated by two and zeros are interlaced in each alternate partition. Then it is followed by component multipliers and adders to get the final product. Based on the application requirement, the component adders and component multipliers can be selected in order to balance area and speed. The proposed system is synthesized using Xilinx tool. Experimental results show that the proposed interlaced separation Vedic multiplier is faster and has greater power efficiency in Field Programmable Gate Array (FPGA) implementation.

Vedic Multiplier, Ripple Carry Adder, FPGA, VLSI

[1] Christopher Fritz, and Adly T. Fam, “Interlaced Partition Multiplier”, IEEE Transactions on Computers, Vol. 65, No. 8, pp. 2652-2658, 2016.
[2] C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Transactions on Electronic Computers, Vol. EC-13, No. 1, pp. 14–17, 1964.
[3] L. Dadda, “Some schemes for parallel multipliers,” Alta Frequenza, Vol. 34, pp. 349–356, 1965.
[4] P. Kogge and H. Stone, “A parallel algorithm for the efficient solution of a general class of recurrence equations,” IEEE Transactions on . Computers., Vol. C-22, No. 8, pp. 783–791, 1973.
[5] H. Eriksson, P. Larsson-Edefors,M. Sheeran, M. Sjalander, D. Johansson, and M. Scholin, “Multiplier reduction tree with logarithmic logic depth and regular connectivity,” in Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, Canada, pp. 4–8.
[6] R. Waters and E. Swartzlander, “A reduced complexity Wallace multiplier reduction,” IEEE Transactions on Computers, Vol. 59, No. 8, pp. 1134–1137, 2010.
[7] M. Schulte and E. Swartzlander, “Parallel reduced area multipliers,” Journal of VLSI Signal Processing Systems, Vol. 9, pp. 181–191, 1995.
[8] E.L.Brawn, “Digital Computer Design”, New York Academic Press, New York, pp. 494-498, 1963.
[9] A.Habibbi and P.A.Wintz, “Fast Multipliers”, IEEE Transactions on Computers, Vol.C-19, pp. 153-157, 1970.
[10] K.C.Bickerstaff, M.J.Schulte, and EE.Swartzlander,Jr., “Reduced Area Multipliers”, Proceedings of the 1993 International Conference on Application Specific Array Processors, USA, pp. 478-489.
[11] D. Naresh, Giri Babu Kande, “High Speed Signed multiplier for Digital Signal Processing Applications”, IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) ,Vol 8, Issue 2 , pp 57-61,2009.
[12] Mohammed Hasmat Ali, Anil Kumar Sahani, “Study, Implementation and Comparison of Different Multipliers based on Array, KCM and Vedic Mathematics Using EDA Tools”, International Journal of Scientific and Research Publications, Vol. 3, Issue 6, 2013.
[13] S.K.Panda, R.Das, S.K.Saifur Raheman, Tapasa Ranjan Sahoo, “VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VHDL Environment: A Novelty”, Vol. 5, No 1, pp.17-24, 2015.
[14] A Debasish Subudhi, Kanhu Charan Gauda, Abinash Kumar Pala, Jagamohan Das,” Design and Implementation of High Speed 4x4 Vedic Multiplier”, International Journal of Advanced Research in Computer Science and Software Engineering, Vol. 4, Issue 11, pp.362-366, 2014.
[15] W. J. Townsend, E. E. Swartzlander Jr., and J. A. Abraham “A comparison of Dadda and Wallace multiplier delays,” in the 2003 proceedings of SPIE. on Advanced Signal Processing Algorithms, Vol. 5205, pp. 552–560.
[16] T. K. Callaway and Jr. E. E. Swartzlander, "Optimizing Multipliers for WSI," in the 1993Proceedings of the Fifth Annual IEEE International Conference on Wafer Scale Integration, USA, pp. 85-94.
[17] Chandan Singh, “Realization of FIR Filter using Distributed Arithmetic Architecture”, International Journal of Scientific Research in Computer Science and Engineering Vol. 3, Issue-4, pp. 7-12, 2015.
[18] Anil Pratap, “Analysis of Full and Half Adder Using Different Logic Style”, International Journal of Scientific Research in Computer Science and Engineering, Vol. 4, Issue.1, pp. 6-9, 2016.