Reversible logic is the promising design methodology for the future quantum circuits. Since there is no loss in information in reversible circuits, it can be used to create the low power design for super computers. Fault Tolerance in reversible logic is required to ensure the design work correctly even in presence of any faults. A majority voter is proposed which achieves the passive hardware redundancy for any reversible circuit, thereby making the circuit Fault Tolerant. Parity preserving feature induced in the majority voter helps to test the voter for any occurrence of faults. A comparative analysis is done for the available reversible benchmark circuits using the proposed Fault Tolerant approach. A fault diagnosis technique to increase the reliability of the majority voter is also proposed.

Fault Tolerance, Quantum, Reversible Logic, Parity Preserving Logic

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