Execution of an Image Scaling Mainframe Via VLSI Procedure
R.Raj Prabhu1 , G.Mary Amirtha Sagayee2
Section:Research Paper, Product Type: Journal Paper
Volume-2 ,
Issue-12 , Page no. 29-33, Dec-2014
Online published on Dec 31, 2014
Copyright © R.Raj Prabhu, G.Mary Amirtha Sagayee . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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IEEE Style Citation: R.Raj Prabhu, G.Mary Amirtha Sagayee, “Execution of an Image Scaling Mainframe Via VLSI Procedure,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.12, pp.29-33, 2014.
MLA Style Citation: R.Raj Prabhu, G.Mary Amirtha Sagayee "Execution of an Image Scaling Mainframe Via VLSI Procedure." International Journal of Computer Sciences and Engineering 2.12 (2014): 29-33.
APA Style Citation: R.Raj Prabhu, G.Mary Amirtha Sagayee, (2014). Execution of an Image Scaling Mainframe Via VLSI Procedure. International Journal of Computer Sciences and Engineering, 2(12), 29-33.
BibTex Style Citation:
@article{Prabhu_2014,
author = {R.Raj Prabhu, G.Mary Amirtha Sagayee},
title = {Execution of an Image Scaling Mainframe Via VLSI Procedure},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {12 2014},
volume = {2},
Issue = {12},
month = {12},
year = {2014},
issn = {2347-2693},
pages = {29-33},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=326},
publisher = {IJCSE, Indore, INDIA},
}
RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=326
TI - Execution of an Image Scaling Mainframe Via VLSI Procedure
T2 - International Journal of Computer Sciences and Engineering
AU - R.Raj Prabhu, G.Mary Amirtha Sagayee
PY - 2014
DA - 2014/12/31
PB - IJCSE, Indore, INDIA
SP - 29-33
IS - 12
VL - 2
SN - 2347-2693
ER -
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Abstract
Image mounting is an actual important technique and has been widely used in many image handling applications. In uses where the mounting procedure must be did at the show somewhat than at the CPU or GPU, committed hardware execution is necessary. Low-difficulty image handling procedures are necessary for VLSI execution of real period applications. The image mounting algorithm of the future scheme covers of an improving spatial filter, a clamp filter, and a Biwrinkled interpolation. Imageries are took in real period by an image instrument and send to the FPGA along with the mounting parameter. Sequential connectivity is if to the FPGA and the scaled imageries are showed on the pc. The select combining, hardware distribution methods of the Biwrinkled interpolator and reconfigurable methods has been used to reduction hardware costs.
Key-Words / Index Term
Improving filter, Actual big gage addition (VLSI),Clamp filter, Image sensor, Biwrinkled interpolation, Reconfigurable deSymbol Component ,FPGA
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