The main objective of this research paper is to design architecture for radix-4 complex Vedic multiplier by rectifying the problems in the existing method and to improve the speed by using the common Boolean logic (CBL). The multiplier algorithm is normally used for higher bit length applications and ordinary multiplier is good for lower order bits. These two methods are combined to produce the high speed multiplier for higher bit length applications. The problem of existing architecture is reduced by removing bits from the remainders. The proposed algorithm is implementation Xilinx software with Vertex-7 device family.

Vedic Multiplier, Complex Multiplier, Common Boolean Logic Adder, Xilinx Software

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