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Improved stability and access time Using Different 6T SRAM Cells at Low Voltage

Ashish Raturi1 , Kamlesh Bhatt2

Section:Research Paper, Product Type: Journal Paper
Volume-7 , Issue-7 , Page no. 298-301, Jul-2019

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v7i7.298301

Online published on Jul 31, 2019

Copyright © Ashish Raturi, Kamlesh Bhatt . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Ashish Raturi, Kamlesh Bhatt, “Improved stability and access time Using Different 6T SRAM Cells at Low Voltage,” International Journal of Computer Sciences and Engineering, Vol.7, Issue.7, pp.298-301, 2019.

MLA Style Citation: Ashish Raturi, Kamlesh Bhatt "Improved stability and access time Using Different 6T SRAM Cells at Low Voltage." International Journal of Computer Sciences and Engineering 7.7 (2019): 298-301.

APA Style Citation: Ashish Raturi, Kamlesh Bhatt, (2019). Improved stability and access time Using Different 6T SRAM Cells at Low Voltage. International Journal of Computer Sciences and Engineering, 7(7), 298-301.

BibTex Style Citation:
@article{Raturi_2019,
author = {Ashish Raturi, Kamlesh Bhatt},
title = {Improved stability and access time Using Different 6T SRAM Cells at Low Voltage},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {7 2019},
volume = {7},
Issue = {7},
month = {7},
year = {2019},
issn = {2347-2693},
pages = {298-301},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=4764},
doi = {https://doi.org/10.26438/ijcse/v7i7.298301}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v7i7.298301}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=4764
TI - Improved stability and access time Using Different 6T SRAM Cells at Low Voltage
T2 - International Journal of Computer Sciences and Engineering
AU - Ashish Raturi, Kamlesh Bhatt
PY - 2019
DA - 2019/07/31
PB - IJCSE, Indore, INDIA
SP - 298-301
IS - 7
VL - 7
SN - 2347-2693
ER -

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Abstract

Contradictory nature of read and write stability and stability with speed necessitates the use of FinFET device which has less statistical variability, sensitivity and more on current. In this work, we explored three different FinFET device structures. These structures are used to form three different 6T SRAM cells. All the simulations are done with the help of Sentaurus TCAD. Three SRAM cells are compared to reduce access time and enhance data stability. We found that ADSE FinFET SRAM achieve significant improvement in access time as compared to Underlap FinFET SRAM cell without degradation of cell stability. On the other hand High-k spacer SRAM cell shows noteworthy increase in stability over other two cells with somewhat slower response.

Key-Words / Index Term

ADSE, FinFET, High-k spacer SRAM, Underlap

References

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