In this paper, we propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage, channel length and gate oxide thickness are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm Technology.

FinFET; Leakage Current; Leakage Power; Static random access memory (SRAM); Self-controllable Voltage Level (SVL); Upper SVL; Lower SVL

[1] K. Bowman, et al., “Impact of die-to-die and within die parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” IEEE J. Solid-State Circuits, vol. 37, no. 2, 2002, pp. 183-190.
[2] S. Borkar, et al., “Parameter variations and impact on circuits and microarchitecture,” ACWIEEE DAC, 2003, pp. 338-342.
[3] T. Karnik, T. De, and S. Borkar, “Statistical design for variation tolerance: key to continued Moore’s law,” in Proc. Int. Conf. Integrated Circuit Design and Technology, 2004, pp. 175-176.
[4] Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M. R. Lin, “15 nm gate length planar CMOS transistor,” in IEDM Tech. Dig., 2001, pp. 937–939.
[5] Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, 2000, pp. 2320–2325.
[6] J. Y. S. Balasubramanium, “Design of sub-50 nm FinFET based low power SRAMs,” Semicond. Sci. Technol., vol. 23, 2008, p. 13-19.
[7] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70 MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply,” in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 474–476.
[8] M.D. Powell, S.H. Yang, B. Falsafi et. al, “Gated – VDD:A circuit technique to reduce leakage in cache memories,” in proceedings of International Symposium on Low Power Electronics and Design, 2000, pp. 90-95.
[9] Amit Agarwal, Hai Li and Kaushik Roy, “DRG Cache: A data retention gated- ground cache for low power,” in proceedings of the 39th Design Automation Conference, 2002, pp. 473-478.
[10] Rafik S. Guindi , Farid N. Najm, “Design Techniques for Gate-Leakage Reduction in CMOS Circuits,” in proceedings of the Fourth International Symposium on Quality Electronic Design, 2003, pp. 61-65.
[11] L. Chang et al., “Stable SRAM Cell Design for the 32nm Node and Beyond,” Symp. VLSI Tech. Dig., 2005, pp. 292-293.
[12] Enomoto, T., Oka, Y., Shikano, H., & Harada, T., “A self-controllable voltage-level (SVL) circuit for low-power, high-speed CMOS circuits,” in Proceedings of European solid-state circuits conference, 2002, pp. 411–414.
[13] K. Kanda, H. Sadaaki, and T. Sakurai, “90% write power-saving SRAM using sense-amplifying memory cell,” IEEE Journal of Solid-State Circuits, vol. 39, 2004, pp. 927–933.
[14] S. Lavanya, and J. Lisbin, “Self controllable voltage level (SVL) for low power consumption” in IEEE International Conference on Computational Intelligence & Computing Research (ICCIC), 2012, pp. 1-5.