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Various Design Architectural level Power Reduction Techniques for Viterbi Decoder: A Review

Jyoti J. Zunzunwala1 , A. S. Joshi2

Section:Review Paper, Product Type: Journal Paper
Volume-8 , Issue-4 , Page no. 85-89, Apr-2020

CrossRef-DOI:   https://doi.org/10.26438/ijcse/v8i4.8589

Online published on Apr 30, 2020

Copyright © Jyoti J. Zunzunwala , A. S. Joshi . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Jyoti J. Zunzunwala , A. S. Joshi, “Various Design Architectural level Power Reduction Techniques for Viterbi Decoder: A Review,” International Journal of Computer Sciences and Engineering, Vol.8, Issue.4, pp.85-89, 2020.

MLA Style Citation: Jyoti J. Zunzunwala , A. S. Joshi "Various Design Architectural level Power Reduction Techniques for Viterbi Decoder: A Review." International Journal of Computer Sciences and Engineering 8.4 (2020): 85-89.

APA Style Citation: Jyoti J. Zunzunwala , A. S. Joshi, (2020). Various Design Architectural level Power Reduction Techniques for Viterbi Decoder: A Review. International Journal of Computer Sciences and Engineering, 8(4), 85-89.

BibTex Style Citation:
@article{Zunzunwala_2020,
author = {Jyoti J. Zunzunwala , A. S. Joshi},
title = {Various Design Architectural level Power Reduction Techniques for Viterbi Decoder: A Review},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {4 2020},
volume = {8},
Issue = {4},
month = {4},
year = {2020},
issn = {2347-2693},
pages = {85-89},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=5080},
doi = {https://doi.org/10.26438/ijcse/v8i4.8589}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v8i4.8589}
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=5080
TI - Various Design Architectural level Power Reduction Techniques for Viterbi Decoder: A Review
T2 - International Journal of Computer Sciences and Engineering
AU - Jyoti J. Zunzunwala , A. S. Joshi
PY - 2020
DA - 2020/04/30
PB - IJCSE, Indore, INDIA
SP - 85-89
IS - 4
VL - 8
SN - 2347-2693
ER -

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Abstract

The Viterbi algorithm is commonly applied in a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. The Viterbi algorithm process is similar to finding the most-likely sequence of states, resulting in sequence of observed events and, thus, boasts of high efficiency as it consists of finite number of possible states. Viterbi decoder is very important part at the receiver side in order to decode the convolutional codes. This paper briefly reviews the power reduction techniques along with their comparative analysis for designing Veterbi decoder at the receiver side of convolutional codes.

Key-Words / Index Term

Viterbi Decoder, BMU, PMU, SMU, ACS

References

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