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Implementation of SHA on FPGA

Ankit Anand1 , Pushkar Praveen2 , Shruti 3

Section:Research Paper, Product Type: Journal Paper
Volume-3 , Issue-5 , Page no. 252-257, May-2015

Online published on May 30, 2015

Copyright © Ankit Anand, Pushkar Praveen , Shruti . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Ankit Anand, Pushkar Praveen , Shruti, “Implementation of SHA on FPGA,” International Journal of Computer Sciences and Engineering, Vol.3, Issue.5, pp.252-257, 2015.

MLA Style Citation: Ankit Anand, Pushkar Praveen , Shruti "Implementation of SHA on FPGA." International Journal of Computer Sciences and Engineering 3.5 (2015): 252-257.

APA Style Citation: Ankit Anand, Pushkar Praveen , Shruti, (2015). Implementation of SHA on FPGA. International Journal of Computer Sciences and Engineering, 3(5), 252-257.

BibTex Style Citation:
@article{Anand_2015,
author = {Ankit Anand, Pushkar Praveen , Shruti},
title = {Implementation of SHA on FPGA},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {5 2015},
volume = {3},
Issue = {5},
month = {5},
year = {2015},
issn = {2347-2693},
pages = {252-257},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=513},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=513
TI - Implementation of SHA on FPGA
T2 - International Journal of Computer Sciences and Engineering
AU - Ankit Anand, Pushkar Praveen , Shruti
PY - 2015
DA - 2015/05/30
PB - IJCSE, Indore, INDIA
SP - 252-257
IS - 5
VL - 3
SN - 2347-2693
ER -

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Abstract

In this paper, an FPGA based SHA1 core is designed and implemented using the hardware description language VHDL. Hash functions are the most important cryptographic algorithms and used in the several fields of communication integrity and signature authentication. These functions produce a fixed-size fingerprint or hash value for a variable length (very long) message. The hash function SHA-1, Secure Hash Algorithm, is examined in order to find the common constructs that can be used to implement it using hardware blocks of the FPGA. As a result, a hash core supporting SHA-1 and having a standard single bit SPI is proposed. The hardware is described using VHDL and verified on Xilinx FPGA.

Key-Words / Index Term

ASIC, Digital Signature, FPGA, Message Digest, SHA, RTL, VHDL

References

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