Relentless scaling to minimum dimensions for achieving higher packing density, reduced power dissipation and aggrandized integrated circuit speed, has made CMOS a prevailing technology for very large scale integration (VLSI) applications in the last few decades. CMOS operational amplifier (Op Amp) as a building block in analogue integrated circuits and mixed signal system has compelled researchers to execute efficient designing model and its analysis. This study was aimed to accomplish the design, simulation and inquisitive behavioral analysis of a Three-Stage OP-AMP at 100 nm technology node using 1 volt as power supply (Vdd). Transfer function, input resistance, output resistance, average power, slew-rate, phase margin, DC gain and many other parameters were duly taken into consideration during simulation processes. High DC gain (69.69 dB), high bandwidth (52.619 KHz), low output resistance (25.0718 ohm.) and low power dissipation were achieved successfully by applying the designed model proposed in the present study which satisfy the requirement of highly efficient Op Amp. This CMOS-dependent-three-stage OP AMP architectonic with various promising specifications is suitable for applying in different amplifier architectures and other related designs in nano level CMOS technology

CMOS, Three-stage op-amp, Low voltage, Transistors, DC gain

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