In this work, a novel quaternary algebra has been proposed that can be used to implement an arbitrary quaternary logic function in more than one systematic ways. The proposed logic has evolved from and is closely related to the Boolean algebra for binary domain; yet it does not lack the benefits of a higher-radix system. It offers seamless integration of the binary logic functions and expressions through a set of transforms and allows any binary logic simplification technique to be applied in quaternary domain. Since physical realization of the operators defined in this logic has recently been reported, it has become very important to have a well-defined algebra that will facilitate the algebraic manipulation of the novel quaternary logic and aid in designing various complex logic circuits. Therefore, based on our earlier works, here we describe the complete algebraic representation of this logic for the first time. The efficacy of the logic has been shown by designing and comparing several common logic circuits with existing designs in both binary and quaternary domain.

Propositional Logic, Quaternary algebra, Quaternary Transformation, Sum-of-products

[1] Hurst, S.L; “Multiple-Valued Logic; its Status and its Future”, Computers, IEEE Transactions on, 33 (12), 1160-1179, (1984)
[2] Miller, D.M.; Thornton, M.A.; “Multiple Valued Logic: Concepts and Representations”, Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, (2007)
[3] Smith, K.C.; “The Prospects for Multivalued Logic- A Technology and Applications View”, Computers, IEEE Transactions on, 30, 619-634, (1981)
[4] Fijany, A.; Vatan, F.; Mojarradi, M.; Toomarian, B.; Blalock, B.; Akarvardar, K.; Cristoloveanu, S.; Gentil, P.; “The G4-FET- a universal and programmable logic gate”, Proceedings of the 15th ACM Great Lakes symposium on VLSI (GLSVLSI 2005), 349-352, (2005)
[5] Keshavarzian, A.P.; Navi, K.; “Optimum Quaternary Galois Field Circuit Design through Carbon Nano Tube Technology”, Proceedings, International Conference on Advanced Computing and Communications (ADCOM 2007), 214-219, (2007)
[6] Balaji, B.; Malik, S. S.; “Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power CMOS VLSI Circuits”, International Journal of Computer Sciences and Engineering, E-ISSN: 2347-2693, 2 (9), 75-77, (2014)
[7] Kahrari, Z.; Karimi, G.; “A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology”, International Journal of Computer Sciences and Engineering, E-ISSN: 2347-2693, 4 (1), 14-16, (2016)
[8] Chattopadhyay, T.; Taraphdar, C.; Roy, J.N.; “Quaternary Galois field adder based all-optical multivalued logic circuits”, Applied Optics, 48 (22), E35-E44, (2009)
[9] Khan, M.H.A.; “Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits”, Engineering Letters, 15 (2), 203-207 (2007)
[10] Falkowski, B.J.; Rahardja, S.; “Generalised hybrid arithmetic canonical expansions for completely specified quaternary functions”, Electronics Letters, 37 (16), 1006-1007, (2001)
[11] Khan, M.H.A.; Siddika, N.K.; Perkowski, M.A.; “Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram”, Proceedings, 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 125-130, (2008)
[12] Khan, M.M.M.; Biswas, A.K.; Chowdhury, S.; Tanzid, M.; Mohsin, K.M.; Hasan, M.; Khan, A.I.; “Quantum realization of some quaternary circuits”, Proceedings, TENCON 2008, IEEE Region 10 Conference, (2008)
[13] Yasuda, Y.; Tokuda, Y.; Zaima, S.; Pak, K.; Nakamura, T.; Yoshida, A.; “Realization of quaternary logic circuits by n-channel MOS devices”, Solid-State Circuits, IEEE Journal of, 21 (1), 162-168, (1986)
[14] Park, S.J.; Yoon, B.H.; Yoon, K.S.; Kim, H.S.; “Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit”, Proceedings, 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 198-203, (2004)
[15] da Silva, R.C.G.; Boudinov, H.; Carro, L.; “A novel Voltage-mode CMOS quaternary logic design”, Electron Devices, IEEE Transactions on, 53 (6), 1480, (2006)
[16] Inaba, M.; Tanno, K.; Ishizuka, O.; “Realization of NMAX and NMIN functions with multi-valued voltage comparators”, Proceedings, 31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001), 27-32, (2001)
[17] Datla, S.R.; Thornton, M.A.; “Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits”, Proceedings, 40th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2010), 128-133, (2010)
[18] Chattopadhyay, T.; Roy, J.N.; “Polarization-encoded all-optical quaternary multiplexer and demultiplexer - A proposal”, Optik - International Journal for Light and Electron Optics, 120 (17), 941-946, (2009)
[19] Vranesic, Z. G.; Waliuzzaman, K. M.; “Functional transformation in simplification of multivalued switching functions”, IEEE Transactions on Computers, 21(1), 102-105 (1972)
[20] Jahangir, I.; Hasan, D.M.N.; Siddique, N.A.; Islam, S.; Hasan, M.M.; “Design of quaternary sequential circuits using a newly proposed quaternary algebra”, Proceedings, 12th International Conference on Computers and Information Technology (ICCIT 2009), 203, (2009)
[21] Das, A.; Jahangir, I.; Hasan, M.; Hossain, S.; “On the design and analysis of quaternary serial and parallel adders”, Proceedings, TENCON 2010, IEEE Region 10 Conference, 1691, (2010)
[22] Jahangir, I.; Das, A.; “On the design of quaternary comparators”, Proceedings, 13th International Conference on Computers and Information Technology (ICCIT 2010), 241, (2010)
[23] Jahangir, I.; Hasan, D.M.N.; Islam, S.; Siddique, N.A.; Hasan, M.M.; “Development of a novel quaternary algebra with the design of some useful logic blocks”, Proceedings, 12th International Conference on Computers and Information Technology (ICCIT 2009), 197, (2009)
[24] Jahangir, I.; Hasan, D.M.N.; Reza, M.S.; “Design of some quaternary combinational logic blocks using a new logic system”, Proceedings, TENCON 2009, IEEE Region 10 Conference, (2009)
[25] Das, A.; Jahangir, I.; Hasan, M.; “Optimization of sum of product expressions in a novel quaternary algebra”, Proceedings, International Conference on Informatics, Electronics & Vision (ICIEV), (2014)
[26] Jahangir, I.; Das, A.; Hasan, M.; “Design of novel quaternary encoders and decoders”, Proceedings, International Conference on Informatics, Electronics & Vision (ICIEV), (2012)
[27] Gogna, P.; Lingalugari, M.; Chandy, J.; Heller, E.; Hasaneen, E.S.; Jain, F.; “Quaternary logic and applications using multiple quantum well based SWSFETs”, International Journal of VLSI design & Communication Systems (VLSICS), 3(5), 27-42 (2012)
[28] Jain, F.C.; Chandy, J.; Miller, B.; Hasaneen, E.S.; Heller, E.; “Spatial wavefunction-switched (SWS)-FET: A novel device to process multiple bits simultaneously with sub-picosecond delays”, International Journal of High Speed Electronics and Systems, 20(03), 641-652 (2011)
[29] Gogna, P.; Suarez, E.; Lingalugari, M.; Chandy, J.; Heller, E.; Hasaneen, E.S.; Jain, F.C.; “Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic”, Journal of electronic materials, 42(11), 3337-3343 (2013)
[30] Chattopadhyay, T.; Roy, J. N.; “All-optical quaternary computing and information processing: a promising path”, Journal of Optics, 42(3), 228-238 (2013)
[31] Huntington, E.V.; “Sets of Independent Postulates for the Algebra of Logic”, Transactions of the American Mathematical Society, 5 (3), 288-309, (1904)
[32] Khan, M.H.A.; “Quantum Realization of Quaternary Feynman and Toffoli Gates”, Proceedings, 4th International Conference on Electrical and Computer Engineering (ICECE 2006), 157–160, (2006)
[33] Khan, M.H.A.; Perkowski, M.A.; “GF(4) Based Synthesis of Quaternary Reversible-Quantum Logic Circuits”, Journal of Multiple-Valued Logic and Soft Computing, 13, 583-603, (2007)