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A Novel Low Power Full Adder Using a Modified Domino Logic

Somayyeh Jafarali Jassbi1 , 2 , Moloud Mousavi3

Section:Research Paper, Product Type: Journal Paper
Volume-4 , Issue-6 , Page no. 8-11, Jun-2016

Online published on Jul 01, 2016

Copyright © Somayyeh Jafarali Jassbi, , Moloud Mousavi . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: Somayyeh Jafarali Jassbi, , Moloud Mousavi, “A Novel Low Power Full Adder Using a Modified Domino Logic,” International Journal of Computer Sciences and Engineering, Vol.4, Issue.6, pp.8-11, 2016.

MLA Style Citation: Somayyeh Jafarali Jassbi, , Moloud Mousavi "A Novel Low Power Full Adder Using a Modified Domino Logic." International Journal of Computer Sciences and Engineering 4.6 (2016): 8-11.

APA Style Citation: Somayyeh Jafarali Jassbi, , Moloud Mousavi, (2016). A Novel Low Power Full Adder Using a Modified Domino Logic. International Journal of Computer Sciences and Engineering, 4(6), 8-11.

BibTex Style Citation:
@article{Jassbi_2016,
author = {Somayyeh Jafarali Jassbi, , Moloud Mousavi},
title = {A Novel Low Power Full Adder Using a Modified Domino Logic},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {6 2016},
volume = {4},
Issue = {6},
month = {6},
year = {2016},
issn = {2347-2693},
pages = {8-11},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=957},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=957
TI - A Novel Low Power Full Adder Using a Modified Domino Logic
T2 - International Journal of Computer Sciences and Engineering
AU - Somayyeh Jafarali Jassbi, , Moloud Mousavi
PY - 2016
DA - 2016/07/01
PB - IJCSE, Indore, INDIA
SP - 8-11
IS - 6
VL - 4
SN - 2347-2693
ER -

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Abstract

A low power and high speed Full adder circuit design using a new CMOS domino logic family is presented in this paper. The presented domino logic is based on Magnetic Tunnel Junction Elements (MTJ) in Gate Diffusion Input (GDI) Technique. Compared to static CMOS logic circuits, dynamic logic circuits are important as it provides better speed and has less transistor requirement. The proposed circuit has very low dynamic power consumption and less delay compared to the recently proposed circuit techniques for the dynamic logic styles. Moreover, it will be shown that the proposed circuit is extremely fault tolerant. The monte carlo simulation is performed to emphasis the fault tolerance of proposed full adder. The proposed full adder is simulated using standard 0.18 um CMOS technology.

Key-Words / Index Term

Domino, Full Adder, Buffer, Low Power

References

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