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Generation of Testcases from UML Sequence Diagram and Detecting Deadlocks using Loop Detection Algorithm

A. Mallick1 , N. Panda2 , A.A. Acharya3

Section:Research Paper, Product Type: Journal Paper
Volume-2 , Issue-3 , Page no. 199-203, Mar-2014

Online published on Mar 30, 2014

Copyright © A. Mallick, N. Panda, A.A. Acharya . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: A. Mallick, N. Panda, A.A. Acharya, “Generation of Testcases from UML Sequence Diagram and Detecting Deadlocks using Loop Detection Algorithm,” International Journal of Computer Sciences and Engineering, Vol.2, Issue.3, pp.199-203, 2014.

MLA Style Citation: A. Mallick, N. Panda, A.A. Acharya "Generation of Testcases from UML Sequence Diagram and Detecting Deadlocks using Loop Detection Algorithm." International Journal of Computer Sciences and Engineering 2.3 (2014): 199-203.

APA Style Citation: A. Mallick, N. Panda, A.A. Acharya, (2014). Generation of Testcases from UML Sequence Diagram and Detecting Deadlocks using Loop Detection Algorithm. International Journal of Computer Sciences and Engineering, 2(3), 199-203.

BibTex Style Citation:
@article{Mallick_2014,
author = {A. Mallick, N. Panda, A.A. Acharya},
title = {Generation of Testcases from UML Sequence Diagram and Detecting Deadlocks using Loop Detection Algorithm},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {3 2014},
volume = {2},
Issue = {3},
month = {3},
year = {2014},
issn = {2347-2693},
pages = {199-203},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=96},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=96
TI - Generation of Testcases from UML Sequence Diagram and Detecting Deadlocks using Loop Detection Algorithm
T2 - International Journal of Computer Sciences and Engineering
AU - A. Mallick, N. Panda, A.A. Acharya
PY - 2014
DA - 2014/03/30
PB - IJCSE, Indore, INDIA
SP - 199-203
IS - 3
VL - 2
SN - 2347-2693
ER -

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Abstract

In an environment where processes those execute concurrently, speeding up their computation is important. Deadlock is a major issue that occurs during concurrent execution. In this paper, we present an approach to generate testcases from UML sequence diagram for detecting deadlocks during the design phase. This will reduce the effort and cost involved to fix deadlocks at a later stage. Our work begins with design of sequence diagram for the system, then converting it to intermediate graph where deadlock points are marked and then traverse to get testcases. The testcases thus generated are suitable for detecting deadlocks.

Key-Words / Index Term

Software testing, Test cases,Sequence diagram, Concurrency, Deadlock

References

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