India has a rich intellectual tradition that evolved since last 5000 years. To our luck much knowledge acquired over this period were kept as ancient scriptures. Vedic Mathematics is the name given to the ancient system of Indian Mathematics which was rediscovered from the vedas by Sri Bharathi Krishna Tirthaji. The whole vedic mathematics is based on sixteen sutras providing unique and simple techniques to various mathematical computations. Processing time, power and hardware are the main challenging aspects in any computer algorithms. Hence high speed mathematical tools are of great demand. Ancient Indian scripts are believed to contain many mathematical shortcuts which can be used to fine-tune computer algorithms. Many researchers found the Vedic multipliers, adders and other vedic tools help in saving resources. In this paper we present various applications of vedic mathematics in Digital Signal Processing and also analyzed computational complexity of various algorithms in digital signal processing using vedic mathematics proposed by different researchers.

Vedic Mathematics, Vedic Sutras, Urdhva Tiryakbhyam Sutra, Digital Signal Processing

[1] Jagadguru Swami Sri Bharathi Krishna Tirathji Maharaja, “Vedic Mathematics or Sixteen Simple Mathematical Formulae from Vedas”, Motilal Banarsidas, Varanasi, India, 1965.
[2] M. Pradhan, R. Panda and S.K. Sahu, “Speed Comparison of 16x16 Vedic Multipliers”, International Journal of Computer Applications Vol. 21, Issue 6, pp.16-19, 2011.
[3] P Saha, D Kumar, P. Bhattacharyya, and A Dandapat, “Reciprocal unit based on Vedic mathematics for Signal processing applications”, International Symposium on Electronic System Design, pp.41-45, 2013.
[4] R. Jamgade, S. Ambatkar and S. Kakde. “Design and Implementation of PN Sequence Generator using Vedic Multiplication”, International conference on Advances in Computer Engineering and Applications (ICACEA) IMS Engineering College, Ghaziabad, India, pp .84-87, 2015.
[5] A. Savadi, R.Yanamshetti, S.Biradar, “Design and Implementation of 64 Bit IIR Filters Using Vedic Multipliers”, International conference on Computational Modeling and Security (CMS 2016), Procedia Computer Science 85 (2016) Elsevier, pp.790-797, 2016.
[6] Jinesh S, Ramesh P, J. Thomas, “Implementation of 64 Bit High Speed Multiplier for DSP Application Based on Vedic Mathematics”, TENCON 2015-2015 IEEE Region 10 Conference, 2015.
[7] S.N.Gadakh, A. Khade ,” Design and Optimization of 16 X 16 Bit Multiplier Using Vedic Mathematics”, International Conference on Automatic Control and Dynamic Optimization Techniques (ICACDOT) International Institute of Information Technology (I2 IT), Pune, pp.460-464, 2016.
[8] Anjana S, Pradeep C ,P. Samuel, “Synthesis of High Speed Floating Point Multipliers Based on Vedic Mathematics”, International Conference on Information and Communication Technologies (ICICT 2014), pp.1294-1302, 2014.
[9] M.Shoba, R.Nakkeeram ,”Energy and Area Efficient Hierarchy Multiplier Architecture Based on Vedic Mathematics and GDI logic”, Engineering Science and Technology, an International Journal, Vol 20, Issue.1, pp 321-331, 2017.
[10] L P Thakare , Dr A Y Deshmukh , “Area Efficient Complex Floating Point Multiplier for Reconfigurable FFT/IFFT Processor based on Vedic Algorithm”, 7th International Conference on Communication, Computing and Virtualization 2016, Procedia Computer Science 79 (2016) Elsevier, pp.434-440,2016.
[11] N R Punwantwar, Dr P N Chatur, “Convolution and Deconvolution Using Vedic Mathematics”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol 4,Issue.6, pp.5216-5223, 2015.
[12] Deepthi P, V.S. Chakravarthi,”Design of Novel Vedic Asynchronous Digital Signal Processor Core”, 2014 2nd International Conference on Devices, Circuits and Systems, pp. 1-5, 2014