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Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders

U.V. Sivaiah1 , P.P.M. Krishnna2 , Y. Devaraju3

Section:Research Paper, Product Type: Journal Paper
Volume-1 , Issue-4 , Page no. 23-28, Dec-2013

Online published on Dec 31, 2013

Copyright © U.V. Sivaiah, P.P.M. Krishnna, Y. Devaraju . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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IEEE Style Citation: U.V. Sivaiah, P.P.M. Krishnna, Y. Devaraju, “Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders,” International Journal of Computer Sciences and Engineering, Vol.1, Issue.4, pp.23-28, 2013.

MLA Style Citation: U.V. Sivaiah, P.P.M. Krishnna, Y. Devaraju "Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders." International Journal of Computer Sciences and Engineering 1.4 (2013): 23-28.

APA Style Citation: U.V. Sivaiah, P.P.M. Krishnna, Y. Devaraju, (2013). Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders. International Journal of Computer Sciences and Engineering, 1(4), 23-28.

BibTex Style Citation:
@article{Sivaiah_2013,
author = {U.V. Sivaiah, P.P.M. Krishnna, Y. Devaraju},
title = {Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders},
journal = {International Journal of Computer Sciences and Engineering},
issue_date = {12 2013},
volume = {1},
Issue = {4},
month = {12},
year = {2013},
issn = {2347-2693},
pages = {23-28},
url = {https://www.ijcseonline.org/full_paper_view.php?paper_id=28},
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
UR - https://www.ijcseonline.org/full_paper_view.php?paper_id=28
TI - Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders
T2 - International Journal of Computer Sciences and Engineering
AU - U.V. Sivaiah, P.P.M. Krishnna, Y. Devaraju
PY - 2013
DA - 2013/12/31
PB - IJCSE, Indore, INDIA
SP - 23-28
IS - 4
VL - 1
SN - 2347-2693
ER -

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Abstract

This paper presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter these methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to fir filters to reduce power consumption due to this glitching is also reduced. The minimum power achieved is 110mw in fir filter based on shift/add multiplier in 100MHZ to 8taps and 8bits inputs and 8bits coefficients. The proposed FIR filters were synthesized implemented using Xilinx ISE Spartan 3E FPGA and power is analyzed using Xilinx XPower analyzer.

Key-Words / Index Term

Low Power, Booth Multiplier, Folding Transformation

References

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